The present invention relates in general to the field of packet switching networks, and in particular to the field of recovering timing across a packet switching network, such as an Asynchronous Transfer Mode (ATM) network, that transmits fixed length packets or cells.
Certain services to be carried on packet switching network require synchronization between the transmitting source and receiver at a layer in the OSI model above the physical layer, typically the transport or application layers. Examples of these services include voice and video. Some of the services use constant bit rate (CBR) streams carried over a packet switched network. These CBR streams are sequences of packets that contain data generated by a source at a constant bit rate.
The need to recover timing for CBR streams exists to prevent data buffer underflow or overflow in the receiver and thus a loss of data. This synchronization is at a higher layer than the segment-by-segment physical layer timing recovery required of any link in either a packet or circuit switched network.
One technique for recover timing uses a synchronous residue time stamp (SRTS) which U.S. Pat. Nos. 5,260,978 and 4,961,188 describe. The SRTS technique, however, cannot be used unless there is end-to-end physical layer timing synchronization between the source and destination. Many ATM LAN switches do not permit this type of timing distribution, in addition some types of links such as DS-3 carrying ATM also preclude it.
Other techniques seek to derive timing from the packet or ATM layer itself based upon the CBR nature of the packet or cell stream. U.S. Patent Nos. 5,396,492 and 5,287,182 use the fill level of a First In/First Out (FIFO ) buffer at the receiver to indicate whether the recovered clock at the receiving end is too fast or too slow. If the FIFO buffer fill level increases, the receiver clock is too slow; if the FIFO buffer fill level decreases, the receiver clock is too fast.
Unfortunately, these techniques suffer major drawbacks. For example, lost cells cause the FIFO fill level to indicate a fast clock even if the clock is synchronized. Also the fill level technique requires several cells to be buffered in order to operate properly, and the time needed to receive all these cells can be large enough to affect the critical delay requirement for some applications, such as PBX like voice networks. Third, buffer overflow or underflow will also adversely affect the operation of such a system, such as results in under or over reporting of clock rate correction.
There is, therefore, a need for a system that recovers timing from CBR cell transmissions without adversely affecting receiver operation or using SRTS techniques. Such a system should, in addition, not be affected by buffer overflows or underflows in a receiver circuit.